1. Field of the Invention
The present invention relates to a bus system, and particularly to a bus system and a printed circuit board for use in synchronous type control of an information processing device.
2. Description of Related Art
SyncLink of IEEE1596.4 has been known as a standard for a synchronous memory and a synchronous memory system. The synchronous memory system to which the standard is applied will be hereunder described with reference to the accompanying drawings.
FIG. 32 shows the construction of a synchronous memory system to which SyncLink is applied.
The synchronous memory system to which SyncLink is applied comprises plural synchronous RAMs 104a.sub.#1 to 104a.sub.#n (hereinafter merely referred to as "synchronous RAM 104a, in some cases), a memory controller 101a for controlling write-in and read-out of data into and from the synchronous RAM 104a, an address bus 105a, and a data bus 106a.
The address bus 105a is used to input into an input buffer 1042a of the synchronous RAM 104a, addresses, commands, write data and a synchronous clock signal which are output from an output buffer 1012a of the memory controller 101a, and it comprises a bus line for the address, the commands and the write data, and a synchronous clock line for the synchronous clock signals.
The data bus 106a is used to input into the input buffer 1014a of the memory controller 101a read data which are output from an output buffer 1044a of the synchronous RAM 104a.
The address bus 105a is used in ascending numeric order of the synchronous RAMs 104a to the memory controller 101a (i.e., the order from #1 to #n). On the other hand, the data bus 106a is used in descending numeric order of the synchronous RAMs 104a to the memory controller 101a (i.e., the order from #n to #1). With this setting, the sum of the bus length of the address bus 105a between the memory controller 101a and the synchronous RAM 104a and the bus length of the data bus 106a between the memory controller 101a and the synchronous RAM 104a is set to a substantially equal value among all the synchronous RAMs 104a.sub.#1 to 104a.sub.#n.
According to the synchronous memory system to which the SyncLink as described above is applied, in response to the synchronous clock which is output onto the synchronous clock line of the address bus 105a from the memory controller 101a, the synchronous RAM 104a latches the address, the command and the write data which are output onto a bus of the address bus 105b from the memory controller 101a, whereby the synchronous transmission of the address, the command and the write data can be achieved. Further, the sum of the bus length of the address bus 105a between the memory controller 101a and the synchronous RAM 104a and the bus length of the data bus 106a between the memory controller 101a and the synchronous RAM 104a is set to be substantially equal among all the synchronous RAMs 104a.sub.#1 to 104a.sub.#n, so that the memory access latency to each synchronous RAM 104a of the memory controller 101a can be set to a substantially equal value.